| 摘要 |
PURPOSE:To make it unnecessary to designate individual addresses in an I/O address allocating program by generating an address of a RAM, where I/O address information is stored, by a counter. CONSTITUTION:An I/O address decoding circuit 1 consists of an address control part 5 including an 8-bit binary counter 9, a D flip flop 10, and a selector 11 and a RAM circuit part 4 including OR gates 7 and 8 and a RAM 6. When I/O address data is stored in the RAM 6, the selector 11 connects an address signal 12 from a microcomputer 2 to a RAM address signal to inhibit the write to the RAM 6. When the microcomputer 2 executes an I/O instruction, the RAM 6 supplies data designated by an address bus 12 to an external I/O equipment 3.
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