| 摘要 |
<p>PURPOSE:To obtain the result of measuring representing the elapsed time of jitter quantity at every time slot by providing a storage means writing a data representing the time width decided depending on the quantity of phase jitter in a location represented by an address signal indicating a time slot number. CONSTITUTION:When a jitter measuring period is designated at the pulse leading of a set signal at the measurement, a clock pulse train of sampling signal appears in the transmission signal of an AND gate 2 for a pulse leading period in common to both a reference timing signal and a timing signal extracted from the output pulse being the object of measurement. A counter circuit 3 resets the result of count to zero at every leading of the pulse of the reference timing signal, counts the clock pulse of the transmission signal from the gate 2 and sends the data representing the count result to a bus. Further, a counter circuit 4 is reset by the pulse leading of the set signal, counts the pulse of the reference timing signal, generates the result of count representing the time slot number and sends it to a path as an address. A CPU 6 makes a memory circuit 5 write the data to a location shown in the address.</p> |
