| 摘要 |
PURPOSE:To prevent malfunction caused by a transient input of a meaningless signal by holding a digital signal tentatively representing the past logic value over the period until significance is recovered if the combination of logic values of plural digital signals lose the significance transiently. CONSTITUTION:Incoming parallel digital signals 1a-2a are stored tentatively in flip-flops 12,22 provided corresponding to bits at each bit. Data selection circuits 11, 21 select a data stored tentatively in the flip-flops over the period when a holding signal 3b fed from a control means is inputted and select an incoming signal at the outside of the period. The logic value of the data stored tentatively in the flip-flops and the logic value of the incoming signals are compared by comparison circuits 13, 23 in the control means, and then the logic values are dissident, the holding signal 3b is generated from the time over a desired period. Thus, even when the timings of the parallel signals are not arranged, they are arranged and a digital data having the significance is ensured.
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