发明名称 CACHE SUBSYSTEM
摘要 PURPOSE:To stabilize fast response by preserving held contents even after the power supply of a device is stopped, transferring the hold address information to the address table of a cache memory, and storing its data in the cache memory from an external storage device. CONSTITUTION:A cache memory is connected to an address information external input/output device 2 and the external storage device 3; some of data blocks of the device 3 are held in a cache memory access part 13 and their addresses are held in an address information table retrieval part 10 respectively, thereby allowing address information to be transferred between an address information storage part 11 as a nonvolatile storage medium and the device 2 through an external input/output control part 14. Then, the address information table is transferred from the storage part 11 to the retrieval part 10 and corresponding data blocks are loaded from the device 3 on the basis of the information.
申请公布号 JPS62130440(A) 申请公布日期 1987.06.12
申请号 JP19850272063 申请日期 1985.12.03
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SAKURAI NORIHIKO
分类号 G06F12/08;G06F12/12 主分类号 G06F12/08
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