| 摘要 |
PURPOSE:To obtain multilayer interconnection which are freely connectible between wiring layers by forming a through hole for jump wiring simultaneously with through-holes for continuously wiring at every interlayer insulating film, and simultaneously filling both holes with metal. CONSTITUTION:Al-Si wirings 22 are formed on an Si substrate 21 on which a primary device is formed, a PSG layer 23 is superposed, and etched by RIE to simultaneously form holes 24, 25 for continuously wiring and a hole 26 for jump wiring. Ni layers 27-29 are buried in the holes by an electroless plating method. Then, an aluminum layer 30 is covered and patterned to connect the wirings 22 with 30 by the Ni layers 27, 28. A PSG film 31 is deposited, and a hole 34 is formed as the remaining half for first to third layer wiring hole in coincidence with the hole 26 together with holes 32, 33 for continuously wiring. Ni 35-37 are buried in the holes 32-34. Aluminum wirings 38 are eventually formed, connected with the wirings 30 by the Ni 35, 36 and with the wirings 22 by the Ni 37, 29. According to this configuration, the continuous wirings and the jump wirings are simultaneously formed to contract a chip size.
|
