| 摘要 |
PURPOSE:To optimize a writing and erasing voltage, writing and erasing time by incorporating two kinds of test circuits and a test circuit, which impress a voltage corresponding to a supply voltage onto the gate of a memory cell transistor by another mode, to EEPROM. CONSTITUTION:Since an internal booster circuit 1 is made nonoperational, a test circuit 5 which supplies a writing and erasing voltage from an external terminal is tested by a writing and erasing mode and a test circuit 4 for measuring the threshold voltage of a memory cell transistor is tested by a reading mode, there is no need of using an external terminal AE simultaneously for both tests; therefore there is no need of dividing AE into 2 channels. In the test circuit for threshold voltage measurement, correlation between circuits 4 and 5 is obtained by measuring the threshold voltage of the memory cell transistor using test circuits 4 and 5 respectively at the evaluation stage. And if it is arranged to perform the checking only with the test 5 circuit at the time of manufacture, the necessary external terminal is only EE, and for this terminal an ordinary used terminal can be used.
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