发明名称 RATE SEQUENCE CONTROL SYSTEM
摘要 PURPOSE:To simplify the interface signal and the constitution of equipments by connecting a transmission section including a control section and a modulation section by 3 sets of wires and connecting a reception section including a control section and a demodulation section by 3 sets of wires. CONSTITUTION:The control section 1a and the transmission section 3a are connected by three wires a, b and e and the control section 1a and the reception section 4a are connected by three wires c, d and f. Further, the control section 1a is provided with a P/S conversion circuit 1x having a function converting a signal into a 16-bit setting information serial form. Every time a synchronizing signal is sent from the transmission section 3a, the control section 1a drives the P/S converting circuit 1x to use the signal line (a) and to send once 16-bit information serially and the transmission section 3a sends the received 16-bit information to an opposite MODEM repetitively eight times.
申请公布号 JPS62128248(A) 申请公布日期 1987.06.10
申请号 JP19850267676 申请日期 1985.11.28
申请人 FUJITSU LTD 发明人 MIZUTANI YASUNAO
分类号 H04J3/00;H04L27/00;H04L27/18;H04L27/34;H04L27/36;H04L29/06;H04L29/10 主分类号 H04J3/00
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