发明名称 MULTIPLICATION CIRCUIT
摘要 PURPOSE:To execute a multiplication with a double efficiency in a short time without increasing a circuit scale at all by adding a selection circuit at the periphery of a multiplier of conventional type. CONSTITUTION:A multiplier 1 has the same performance as a conventional type of multiplier which performs multiplication between multipliers K1KN and multiplicands L1-LN and outputs multiplication results M1-M2N-1. A selector 2 is a selector provided at the multiplicand input side of the multiplier 1, and outputs an input A to an output Y when a select input S is 0, and an input B to the output Y when the select input S is 1. 0 is always inputted to the MSB input A of the selector 2, and multiplicands l1-lN are inputted to the input terminal of the selector 2. A selector 3 is a selector provided at the multiplication result output side of the multiplier 1, and similarly as the selector 2, it outputs the input A to the output Y when the select input S is '0', and the input B to the output Y when the select input S is '1'. 0 is always inputted to the LSB input A of the selector 3.
申请公布号 JPS62128334(A) 申请公布日期 1987.06.10
申请号 JP19850268328 申请日期 1985.11.30
申请人 NEC CORP 发明人 HIRAGUCHI MASAYOSHI
分类号 G06F7/533;G06F7/52 主分类号 G06F7/533
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