| 摘要 |
<p>PURPOSE:To suitably avoid erroneous action, etc., due to an unnecessary resetting by dividing a logical block and preventing the resetting of a part of it by a resetting signal due to a certain resetting factor. CONSTITUTION:When a runaway is detected by a runaway detecting circuit 4, a resetting signal is generated and inputted to an OR gate 5. The resetting signal is outputted through an inverter 13 to a resetting output terminal 14. The OR gate 5 to input a system resetting signal and a resetting signal is connected to the first type of a logical block such as a timing controller 6, a register 7. A flip-flop 12 is to show by what resetting signal a microcomputer 1 is reset, a power source VDD is inputted to a data input edge D, the resetting signal from the runaway detecting circuit 4 is inputted to a clock input edge phi, and the system resetting signal is inputted to a resetting input edge R.</p> |
