Multi-signal processor synchronized system.

摘要

The system is made to concentrate n voice signals over a same high speed channel using a single Unit Processor. The data transfers between the Unit Processor and a set of Signal Processors are managed by a counter loaded by the Unit Processor with a predetermined value selected according to the system architecture. The counter is made of two parts serially connected , the first one made for sequentially providing an interrupt request to the Unit Processor and the second one driving a decoder providing signals for serially scanning the set of signal processors and providing time slots for data transfers between Unit Processor and Signal Processors.