发明名称 DETECTING CIRCUIT FOR ABNORMALITY OF CLOCK SIGNAL
摘要 <p>PURPOSE:To detect the abnormal state of a PM clock signal by detecting the disconnection of the 2nd clock signal while a phase modulated clock signal of the 1st frequency is transmitted by means of the 2nd clock signal of the 2nd frequency. CONSTITUTION:A signal state output circuit 115 holds the logic state of the 2nd clock signal 111 of a frequency f1 for a prescribed period in response to the timing of the 2nd clock signal 113 of a frequency f2(>f1) which is used for transmission of the signal 111. A signal state detecting circuit 119 detects the signal state in response to the output signal of the circuit 115. The 2nd clock abnormality detecting circuit 121 detects the abnormal state of the signal 113 and produces a detection output signal 125. An abnormality deciding circuit 127 decides the abnormality of the signal 111 in response to the output signals of both circuits 119 and 121. In such a constitution, the abnormal state of the signal 111 is detected through the total constitution of an abnormality detecting circuit.</p>
申请公布号 JPS62128634(A) 申请公布日期 1987.06.10
申请号 JP19850268519 申请日期 1985.11.29
申请人 FUJITSU LTD 发明人 OZAKI TAKAYUKI
分类号 H04L7/00 主分类号 H04L7/00
代理机构 代理人
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