| 摘要 |
PURPOSE:To improve reliability of the titled system by providing a time slot acquisition error control circuit to a time slot assigning device and disconnecting a faulty processing unit from a bus when a time slot is stacked due to the faulty processing unit to transfer the program to the assignment of the next time slot. CONSTITUTION:The time slot is assigned sequentially to, e.g., processing units 12-l-12-n. When the time slot is stacked due to the faulty processing unit 12-n while the processing unit 12-n is under communication with other processing unit after the acquisition of the time slot, the time slot assigning device 11 detects the error by supervising a time slot acquisition signal to disconnect the faulty processing unit 12-n. After the unit is disconnected from a common bus 10 by the command through a control signal line the time slot is assigned to the next processing unit 12-l.
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