| 摘要 |
A serial pulse frequency converter is disclosed of the type which counts high frequency clock pulses between input pulses, multiplies each successive count by first and second proportionally constants and downcounts the products by high frequency clock pulses to produce output pulses at a new, proportional frequency. A first serial register is used to both count the high frequency pulses between input pulses and hold the count during the multiplication process. It is loaded at the end of multiplication with the a number representing the "lost counts" as it is switched to its counting mode. A second serial register accumulates the sum of partial products of the count and the proportionality constants. The gain circuit serially provides a first proportionality constant and then a second, but may selectively substitute a binary number representing a constant unity for the second. A low frequency detect circuit disables the output if a one is detected in the most significant bit of the first serial register and does not reenable the circuit until two consecutive zeros are detected in the bit. This allows the use of certain economical circuitry in the partial product accumulation and downcounting circuitry which produces accurate results as long as the most significant bit of the registers is zero.
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