发明名称
摘要 PURPOSE:To realize rewriting into main storage (MS) without entailing the special enlargement of hardware and the complication of control by writing data after correction into buffer storage (BS) when a correctable fault is detected in a read of MS and by sending it as store data to MS. CONSTITUTION:Data read out of MS and transferred to BS3 enters BDIR register 2 by way of bus 1 and is written in BS3. The readout address of MS is stored in ADR register 4 previously and then converted into the write address of BS, which is set in BAR register 5 to obtain the BS write address. Data on bus 1, on the other hand, is sent to operator ALU via BDOR register 6 and used as arithmetic data. If a correctable fault is detected during an MS read, the data transferred via bus 1 is set in SDR register 7 as well and used as data for rewriting in MS. For its address the contents of ADR register 4 are set in SAR register 8 and used as that for rewriting in MS.
申请公布号 JPS6226492(B2) 申请公布日期 1987.06.09
申请号 JP19800043592 申请日期 1980.04.04
申请人 HITACHI LTD 发明人 OKABAYASHI MITSUSHI
分类号 G06F12/16;G06F11/00;G06F12/08 主分类号 G06F12/16
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