| 摘要 |
<p>PURPOSE:To attain speed conversion with buffer capacity smaller than data length by partially superposing the writing time of data in a buffer memory to the reading time of data to control data write/read in/from the buffer mem ory. CONSTITUTION:The titled circuit is provided with a buffer memory 1 and a timing forming circuit 2 and the timing forming circuit 2 generates a timing signal on the slave timing side, e.g. the line side, synchronously with a timing signal on the master timing side, e.g. the high way side, and controls data writing/reading time in/from the buffer memory 1 so as to partially superpose these time synchronously with these timing signals. Since the succeeding data can be written in a part of areas whose reading is completed by writing/reading data in/from the buffer memory 1 so that data writing and reading time can be partially superposed, speed change can be attained with the buffer capacity less than that corresponding to the data length to be changed at its speed.</p> |
