| 摘要 |
PURPOSE:To attain the improvement of alignment precision of a semiconductor wafer by a method wherein an alignment mark for the wafer is formed by combining a line space pattern and a double chevron-shaped pattern in a state that the horizontal straight lines of the line space pattern and the oblique straight lines of the chevron- shaped pattern are intersect and the line space part reduces the effect of the flow of a resist at the time of application of the resist to avoid the asymmetrical property of that coating. CONSTITUTION:Line space patterns are exposed on double chevron-shaped patterns exposed in a first shot (a) in a second shot (b) using a mask for semiconductor wafer exposure in a constitution wherein the double chevron-shaped patterns are arranged along the opposed sides of a real element area and the line space patterns are arranged outside of these patterns, and at the same time, the double chevron-shaped patterns are exposed on the line space patterns exposed in the first shot (a) in the second shot (b). Then, the line space patterns are exposed on the double chevron-shaped patterns exposed in the second shot (b) in a third shot (c), and at the same time, the double chevron-shaped patterns are exposed on the line space patterns exposed in the second shot (b) in the third shot (c). In such a way thereafter, the combined pattern of both patterns is formed on the scribed line between the shot and the shot in every shot. |
