| 摘要 |
PURPOSE:To decrease the effect of parasitic capacitance on the potentials of wirings relatively and to decrease a distance between the wirings and the area of the wirings with erroneous operations of elements being avoided, by providing conductors, which are connected to a fixed potential in an insulator, and forming capacitors between said conductors and the conductor wirings. CONSTITUTION:A pair of conductor wirings 15 and 16 is connected to a power source 20 through the channels of P-MOSs T18 and T19 and grounded through the channels of N-MOSs T21 and T22. Namely, the conductor wiring 15 is connected to the drain sides of the P-MOS T18 and the N-MOS T21. Meanwhile, the conductor wiring 16 is connected to the drain sides of the P-MOS T19 and the N-MOS T22. In the gates of the P-MOSs T18 and T19, a clock signal PHI2 is inputted. Input signals I3 and I4 are inputted to the gate of the N-MOSs T21 and T22. A capacitor C3 is formed between a pair of the conductor wirings 15 and 16 at this time. Capacitors are also formed between the conductor wirings 15 and 16 and the conductor wiring 13.
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