发明名称 CONTROL SYSTEM FOR MEMORY SHARED AREA
摘要 PURPOSE:To attain the effective distribution of memories for each system by providing a rewritable register to which an address area showing a shared memory area of a master processor can be set to each slave processor. CONSTITUTION:A master processor 11 gives a rewriting instruction of an address register to the slave memories 16-18 of slave processors 12-14 in a program loading mode. Then a shared memory area 22' is increased and the programs are written directly to the memories 16-18 from the processor 11. When the program loading action is through, an address register is rewritten. Then the memory device 22' is reduced down to a memory area 22. Thus the programs are loaded into the areas out of the shared memory areas of memories 16-18. As a result, the program loading time is shortened and at the same time the using range of a master memory 15 can be set in accordance with a working system, and the effective distribution of memories is attained.
申请公布号 JPS62125444(A) 申请公布日期 1987.06.06
申请号 JP19850264751 申请日期 1985.11.27
申请人 HITACHI LTD 发明人 SAKURAI SHIGERU
分类号 G06F15/16;G06F12/00;G06F12/06;G06F15/167;G06F15/177 主分类号 G06F15/16
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