| 摘要 |
PURPOSE:To reduce man-hours for designing a testing pattern and shorten testing hours, by enabling signals to be directly sent from and received to output terminals without passing through a logic circuit group from input terminals. CONSTITUTION:Input signals inputted to data input terminals 1a-1d are inputted respectively through input buffers 3a-3d to input terminals 4a-4d of a logic circuit group 4. Output signals outputted from output terminals 4e-4h of the circuit group 4 are inputted respectively to input terminals 6a of selector circuits 5a-5d. And, a selector signal inputted to a selector control terminal 2 is inputted through an input buffer 3e to input terminals 6c of selector circuits 5a-5d. Therefore, in a normal operation, output signals from the output terminals 4e-4h of the logic circuit group 4 are outputted respectively through the selector circuits 5a-5d and the output buffers 7a-7d to output terminals 8a-8d. Then, in a testing mode, input signals inputted to the data input terminals 1a-1d are outputted respectively through the input buffers 3a-3e, the input terminals 6b of selector circuits 5a-5d, the output terminals 6d, and the output buffers 7a-7d to the output terminals 8a-8d.
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