| 摘要 |
PURPOSE:To relieve the load on a CPU by writing a data sent to each channel in a RAM, reading the data by an address counter, switching an analog switch and sending the data to a hold circuit of each channel. CONSTITUTION:A buffer control circuit 5 activates a buffer 3 to feed a write address in the RAM2. A CPU1 issues a data, which is written in the RAM2. In reading the data from the RAM2, a buffer 4 is activated and a read address from a counter 7 is supplied to the RAM2. The data read from a D/A converter 10 is subject to D/A conversion and outputted to an analog switch 9 via a voltage follower 11. The analog switch 9 responds to a switch control signal to feed an output of the D/A converter 10 to a sample-and-hold circuit 14.
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