| 摘要 |
PURPOSE:To obtain phase information on a specific signal obtained from a synchronization system for the specific signal with high precision by constituting a PLL loop by using the phase information as a reference signal. CONSTITUTION:The loop LP 1 composed of an adder 1 and a delay circuit 2 performs arithmetic operation based upon a specific expression and the phase of a PN signal having a fixed error component is obtained as the sum output of the adder 1. The phase of the PN signal obtained by a PN locked loop as the reference signal is supplied to an adder 3 firstly and the phase of a PN signal obtained on a carrier is supplied, so that the difference between the both is frequency-divided to, for example, 1/x by a loop filter 4. The frequency division result value is supplied to an adder 5, which subtracts the frequency division value of the PN signal supplied from the adder 1, so that the obtained phase of the PN signal is supplied to the adder 3. Consequently, the PLL loop LP 2 is constituted to remove the fixed removal part.
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