发明名称 BUS CONTROL SYSTEM
摘要 PURPOSE:To improve the bus transfer efficiency by carrying out the bus allocation control after analyzing the bus use request signal given from each unit and the bus control signal including the bus sequence information and attaining the time-division use of the bus. CONSTITUTION:A bus control circuit 3 receives the bus request signals 411, 412 and 41N from N pieces of units and processes them by the prescribed priority in case every unit occupies no bus. In case a bus using request is given from a unit while another bus is occupying a bus, the circuit 3 analyzes the bus using request signal as well as the bus control signal including the bus sequence information supplied from the unit occupying the bus. Then the circuit 3 transmits the acception signal (bus use permitting signal) to the requested unit in the sequence where this unit has no collision against the occupying unit on a bus. Thus the bus allocation control is carried out after analysis of the bus using request signal and the bus control signal for the time-division use of buses. As a result, the bus transfer efficiency is improved.
申请公布号 JPS62123547(A) 申请公布日期 1987.06.04
申请号 JP19850265779 申请日期 1985.11.25
申请人 NEC CORP 发明人 ISHIKAWA ATSUSHI
分类号 G06F13/372;G06F13/20 主分类号 G06F13/372
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