| 摘要 |
Apparatus for asynchronous reception of high-speed data in packet form in a receiver in a telecommunication system where transmitter and receiver are in communication in selected time slots over a common bus. The apparatus includes a delay line (7) receiving the incoming signal and having a plurality of taps, each of which feeds the signal to its own shift register. A locking circuit (10) is furthermore arranged, which stops the stepping forward in the shift register when the first "one" therein has come to a given position, and counting means (12) which senses this given position in each shift register and sums the sensed "ones". A comparison circuit (14) compares the obtained sum with a value constituting the criterion for the number of sensed "ones" representing a received "one". |
