发明名称 DELAY LINE
摘要 PURPOSE:To obtain an adjustable delay time without the provision of an external electrode terminal corresponding to each delay section by providing selectors corresponding to plural delay circuit networks where delay sections are connected in cascade. CONSTITUTION:An L-shaped circuit comprising an inductor 16 and a capacitor 17 is formed at a delay section. A delay line consists of two delay circuit networks each consisting of 4-stage of delay sections, and a selector 4a corresponding to the 1st delay circuit network selects an output of the 3rd delay section by using a control signal from an external control signal input terminal 6a, the output is outputted from an output terminal 7a of the selector 4a and inputted to an input terminal 8 of the 2nd delay circuit network. Further, a selector 4b corresponding to the 2nd delay circuit network selects an output of the 2nd delay section by using a control signal from an external control signal input terminal 6b to select the output of the 2nd delay section and to output the output from an output terminal 7b of the selector 4b and further from an output lead terminal 12 of the delay line.
申请公布号 JPS62122310(A) 申请公布日期 1987.06.03
申请号 JP19850262825 申请日期 1985.11.21
申请人 NEC CORP 发明人 KOBAYASHI KENJI
分类号 H03H7/32 主分类号 H03H7/32
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