发明名称 DISTORTION COMPENSATING CIRCUIT OF VCR OF FET
摘要 PURPOSE:To compensate the distortion of a signal caused when an input signal of a VCR of an FET is large by supervising a signal inputted to a drain of the FET on a control voltage inputted to the gate of the FET. CONSTITUTION:The titled circuit is a voltage controlled variable attenuator comprising a resistor 1 and a VCR of the FET 2 connected in series and controlling the attenuation of an output signal Vo to an input signal V1 by using a control voltage Vc applied between the gate and source of the FET 5. Since the input voltage V1 is superimposed on the control voltage Vc by a capacitor 3 and resistors 4, 5, a drain-gate resistance (gammaDS) fluctuation waveform 7 is obtained corresponding to a VGS waveform 6 as the gate-source voltage based on the superimposed input signal voltage V1. In selecting the resistors 5, 4 to bring the signal level of the input signal voltage V1 superimposed on the control voltage Vc to a proper value, the VGS waveform 6 and the gammaDS fluctuation waveform 7 are operated oppositely mutually and cancelled together, its gammaDS synthesis waveform 10 is made flat to compensate the distortion of the output signal voltage Vo.
申请公布号 JPS62122313(A) 申请公布日期 1987.06.03
申请号 JP19850261030 申请日期 1985.11.22
申请人 HITACHI LTD 发明人 YABUTA KEIZO
分类号 H03G1/04;H03G3/10;H03H11/24 主分类号 H03G1/04
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