发明名称 |
Multiplexed PSK demodulator |
摘要 |
An improved quadrature differential phase shift keyed signal demodulator for use in a modem is shown. A delay circuit (12) delays an input signal for a portion of a baud time. Synchronous detectors (21, 23) mix the original and delayed input signals with coherent reference signals to obtain detected outputs which are alternately provided to a processor (60) by a multiplexer (25). The processor (60) determines the phase shift and provides the demodulated data. An offset baud clock phase locked loop (40) provides a baud clock which is offset by a ninety degree phase lag. The offset baud clock caused the multiplexer (25) to provide detected outputs to the processor (60) for the center one-half of each baud. The result is a demodulator with fewer components and an improved data error rate.
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申请公布号 |
US4670887(A) |
申请公布日期 |
1987.06.02 |
申请号 |
US19850762218 |
申请日期 |
1985.08.05 |
申请人 |
HAYES MICROCOMPUTER PRODUCTS, INC. |
发明人 |
HEATHERINGTON, DALE A. |
分类号 |
H04L27/227;(IPC1-7):H03D3/22;H04L27/22 |
主分类号 |
H04L27/227 |
代理机构 |
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