发明名称
摘要 PURPOSE:To obtain an electrical elimination type P-ROM with one FET by a method wherein an eliminating electrode layer is formed on a field insulating film which seperates a gate insulating film at a certain interval and a floating gate and a control gate which are insulated and overlapped each other are formed and the insulating film under the eliminating electrode is made thicker than that under the floating gate. CONSTITUTION:A field oxide layer 13 is formed on a P type Si substrate at a certain interval and a gate oxide film 12 is separated. On the field oxide film 13 an extension of a poly Si eliminating gate 14 is formed. A floating gate 15 is formed on the gate oxide film and is extended so as to overlap partially the eliminating gate 14 with an oxide film 16 in between. On the floating gate 15 a control gate 18 is formed with poly Si with an oxide film 17 in between. An oxide film under the eliminating gate 14 is formed thicker than the gate oxide film even the oxide film is not the field insulating film. With the above configuration one memory cell can be formed with one FET and the data can be eliminated electrically, so that when the above configuration is applied to P- ROM it will be very effective.
申请公布号 JPS6225274(B2) 申请公布日期 1987.06.02
申请号 JP19800168618 申请日期 1980.11.29
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 MASUOKA FUJIO
分类号 H01L21/8247;H01L29/78;H01L29/788;H01L29/792 主分类号 H01L21/8247
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