发明名称 DELAY TIME EQUALIZING CIRCUIT
摘要 PURPOSE:To make the delay time characteristic and the amplitude characteristic without using an amplitude equalizing circuit by connecting a resistor in series or in parallel with one coil or more and capacitor forming a reactance element additionally. CONSTITUTION:Two capacitors 11, 12 are connected in series, a coil 13 is connected in parallel with the capacitors 11, 12, one terminal of a series circuit comprising a coil 14 and a capacitor 15 whose other terminal is grounded is connected to the midpoint of the capacitors 11, 12. Then a resistor 17 is connected in parallel with the coil 13 and a resistor 18 is connected in parallel with the coil 14. Since a delay time equalizing circuit 1 constituted as above has a maximum passing loss near the frequency maximizing the delay time quantity, a projected amplitude frequency characteristic is provided and the passing loss is adjusted by selecting the resistors 17, 18 properly.
申请公布号 JPS62120709(A) 申请公布日期 1987.06.02
申请号 JP19850261761 申请日期 1985.11.20
申请人 NEC CORP 发明人 OBA HIDEO
分类号 H03H7/01;H03H7/19 主分类号 H03H7/01
代理机构 代理人
主权项
地址
您可能感兴趣的专利