| 摘要 |
PURPOSE:To improve the vector processing efficiency by securing the priority of a store access request for store data that is already stored in a store data buffer or under the control of storage. CONSTITUTION:An address generating part 103 produces a store address for each element of the vector data to send a request address to a priority deciding circuit 201 of a memory controller 2 and also supplied some of those store addresses to a store address processing part 104. The part 104 recognizes the idle state of a store data buffer 206 and reads the store data out of a vector register 105 to send it to the controller 2. A buffer control part 207 of the controller 2 receives the tore data transmission signal and decides a write address to write the store data on the buffer 206. While the part 207 receives the store data transmission signal and informs it to the circuit 201. The circuit 201 secures the priority of the corresponding element and sends the store data to a main memory 3 from the buffer 206.
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