发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PURPOSE:To reduce and shorten wiring by dividing an inspecting circuit and an error correcting circuit, connecting each inspecting circuit to error correcting circuit by a syndrome output line, checking errors by each inspecting circuit and syndrome output line, and correcting errors by each error correcting circuit. CONSTITUTION:Each information block 12 is connected from a sense amplifier 19 to error correcting circuits 21 through wiring 14, and at the same time, connected to error correcting circuits 21 through parity inspecting circuits 20 and a syndrome bus (output line) 22. The syndrome bus 22 connects the parity inspecting circuits 20 and inspecting blocks 13 to combine them successively and connected 6 to each error correcting circuit 21 branching successively. As the syndrome bus 22 is constituted of (n-k) bit wiring, chip are required for wiring can be made small, and concentration of wiring can be prevented.
申请公布号 JPS62119800(A) 申请公布日期 1987.06.01
申请号 JP19850259973 申请日期 1985.11.19
申请人 NEC CORP 发明人 ADACHI TAKAO
分类号 G11C29/00;G06F11/10;G11C29/42 主分类号 G11C29/00
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