| 摘要 |
PURPOSE:To ensure a speedy testing by a method wherein the test of a given basic gate cell in a gate array LSI may be accomplished irrespective of the behavior of a logic circuit. CONSTITUTION:A basic gate cell Gi is constituted of a NAND or NOR gate and connection is made to customers' specifications for the realization of a prescribed logical behavior. An access means Ali is constituted of an AND gate and an emitter of a multi-emitter transistor is used. A plurality of row-selecting lines Sci is selected by a selecting means SC for a test and a plurality of column-selecting lines Sli is selected by a selecting means SL for a test. A read line Mi is connected to the output of a basic gate Gi with the intermediary of a diode DI for monitor by a monitoring means M. In this way, a basic gate Gi is incorporated into a test circuit that is totally different from a logic circuit built to customer's specifications. Access to each basic gate Gi is selectively gained by using an access means Ai irrespective of customers' logic circuits, a signal from an access means forces the output of each basic gate into a certain logical status without affecting the other basic gates for the monitor and test of the output of the gate made access to. With a device designed as such, a prescribed pattern may apply to testing, ensuring a speedy testing.
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