| 摘要 |
PURPOSE:To improve a cache hit rate and to reduce the overhead of a system bus by using a dual port RAM as a main memory to transfer the serial data to a cache memory and also to attain the parallel input of the block transfer information. CONSTITUTION:A hit state is secured when the information on the instruction address of a local address bus LAB is compared with the information on an address tag register ADTAG by a comparator ADC after the instruction fetch cycle of a CPU is started. Under such conditions, the access is discontinued to a system bus and an instruction is fetched from a cache memory. While in a non-hit mode a block transfer request DTR, etc., given from the comparator ADC is inputted to a parallel port of a main memory MM of a RAM in a dual port. Thus an instruction block is transferred to the cache memory from a serial port of the memory MM. The block data are transferred at a high speed via the dual port. Thus it is possible to reduce the overhead to the system bus and to transfer a large quantity of block data. This improves the cache hit factor.
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