| 摘要 |
PURPOSE:To manage the stack levels in terms of hardware and to prevent the malfunction due to an interruption by providing a means to inhibit the interruption when the stack nesting level is maximum. CONSTITUTION:The contents (0 or 1) of the stack pointer 1 of an information processor are decoded by a decoder 2 and the lowest and highest stack levels are first added to a program counter. A stack highest level register 5 stores the highest level and a comparator 4 checks the coincidence between the present level and the highest (allowable) level of the register 5 at every time the contents of the pointer 1 are increased. When the coincidence is obtained between both levels, a signal 7 is applied to an AND gate. Then an interruption inhibition signal 8 is outputted owing to the AND with an interruption input 6. Thus the second saving is avoided to the stack received the saving after the end of the interruption. This prevents the occurrence of the malfunctions due to the interruptions.
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