| 摘要 |
PURPOSE:To obtain a semiconductor integrated circuit characterized by a simple design and few design errors without considering the power consumption amount of a power source wiring, by forming the power source wiring only with the uppermost metal wiring layer of multilayer interconnection layers. CONSTITUTION:A power source wiring is formed only with third metal wirings 10A and 10B, which are the uppermost wirings. A-F are logic function blocks and G is a peripheral block. The power source wirings are formed on the entire surface of the logic function blocks with a wide width. The design can be performed without considering the amount of power consumption. The third metal wiring layers 10A and 10B are connected by a lower wiring layer by way of fourth connecting holes 9A and 9B, which connect the first metal wiring layers and the third metal wiring layers 10A and 10B, so that, e.g., a potential is applied to the source of an MOSFET, which is formed in A-F. |
