| 摘要 |
System providing coherence for the contents of a cache memory having at least one central memory and a multitude of processors, each having a cache memory, in which each of the processors comprises: a purge addresses network means 105 for keeping a copy of the addresses network in which invalidity is sought, in response to the storage in the central memory MC from another processor, the data of the corresponding block in the cache memory from its own processor; an address conversion means 102 for updating a page table word MTP after the address conversion and for storing the updated page table word not in the cache memory but only in the central memory; a signal generator means for producing a page table word storage notification signal in order to give notification, when the address conversion means stores this updated word in the central memory, of the storage of this word, and a purge addresses network 105 invalidating a means which has to be sought and in order to invalidate, in response to the supply of this notification signal and at the actual memory address of this word, originating from its own processor, the data from the corresponding block in the cache memory of its own processor in such a way as to invalidate the data of such a corresponding block.
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