发明名称 ARITHMETIC SYSTEM FOR PROGRAMMABLE CONTROLLER
摘要 PURPOSE:To increase the I/O address points with the minimum memory capacity in response to the size of a controlled system without increasing the length of an instruction word and at the same time to attain the fast arithmetic processing, by using two program memories to store the instruction words. CONSTITUTION:An instruction register 16 consists of an arithmetic code OP which defines the type of arithmetic and an operator LOC which designates an I/O address and reads the data DD1 of a main program 14. While an n-bit shift register 17 contains an operator offset LOCOFST. An I/O address buffer 18 defines its upper bit as the operator LOC and has its single lower bit consisting of a single upper bit LOCOFST1 to be shifted among the operator offsets LOCOFST. In other words, an operator offset LOCOFST1 is added to the operator LOC in terms of the I/O address that controls a part to be controlled. This means that the I/O address points are doubled.
申请公布号 JPS62117002(A) 申请公布日期 1987.05.28
申请号 JP19850256676 申请日期 1985.11.18
申请人 TOSHIBA MACH CO LTD 发明人 KATSUMATA MITSUO
分类号 G06F13/14;G05B19/02;G05B19/05 主分类号 G06F13/14
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