发明名称 MULTICHANNEL TESTING-MACHINE SYNCHRONIZING CIRCUIT
摘要 Quickly synchronizing adjustable delay circuits for a multiple channel tester by using a timing pulse that has reached the end of a given path in the tester to trigger the following timing pulse of a timing generator, thereby providing oscillating timing pulses having an associated frequency related to the propagation delay associated with the particular path, comparing the associated frequency with a reference frequency and adjusting a delay provided in the path until the associated frequency matches a desired frequency.
申请公布号 JPS62116275(A) 申请公布日期 1987.05.27
申请号 JP19860261749 申请日期 1986.11.01
申请人 TERADYNE INC 发明人 JIYOSEFU FURANSHISU RIN;ROORENSU DANIERU HERAA;JIAN NEN CHIEN;JIYAKURIIN NADEIN BURENAA
分类号 G01R31/28;G01R31/317;G01R31/319;H03K5/135;H03K5/1534 主分类号 G01R31/28
代理机构 代理人
主权项
地址