发明名称 MULTIPLEX PROCESSOR SYSTEM
摘要 PURPOSE:To improve the cache hit rate by applying process dispatching processing so that a CPU executing the own process finally causes the execution state as much as possible so long as control based on the priority is not disturbed. CONSTITUTION:When no process under execution exists in CPUs 200-203 or a new process is enqueued in an executable process quene, the process dispatching processing is started. Then the process dispatching processing is informed to the CPU 200, and whether or not a VACANT flag (a flag representing the absence of a process under execution) is logical 1 is decided, and when the flag is 1, the head of the executionable process queue is dequeued. Then PCB (a process control block having an identification name of a CPU executing the process finally) information of the process is fetched in the inside of the CPU 200 and required flag is reset. Thus, the cache hit rate after the process dispatching processing is improved.
申请公布号 JPS62115567(A) 申请公布日期 1987.05.27
申请号 JP19850256287 申请日期 1985.11.15
申请人 NEC CORP 发明人 NOMURA NAOYUKI
分类号 G06F15/16;G06F9/46;G06F9/50;G06F12/08;G06F15/177 主分类号 G06F15/16
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