发明名称 Voltage level detector/holding circuit
摘要 The voltage level detector/holding circuit exhibits a) a comparator having a first and a second input connection and an output connection, the first input connection responding directly to a continuously variable input voltage, b) an analog multiplexer, by means of which the input voltage is applied to the second input connection of the comparator, the analog multiplexer exhibiting a control connection which, in dependence on the voltage at the output connection of the comparator, creates a conducting path through the analog multiplexer when a predetermined ratio exists between the voltages at the first input connection and at the second input connection of the comparator, and c) a capacitor, one electrode of which is connected between the analog multiplexer and the second input connection of the comparator, and the other electrode of which is connected to earth.
申请公布号 DE3640074(A1) 申请公布日期 1987.05.27
申请号 DE19863640074 申请日期 1986.11.24
申请人 NEC CORP. 发明人 IGARASHI,HATSUHIDE;HINOOKA,KIYONOBU
分类号 G01R19/04;(IPC1-7):G01R19/04 主分类号 G01R19/04
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