发明名称 CONTROL PULSE GENERATION CIRCUIT
摘要 <p>PURPOSE:To obtain a control pulse with a simple circuit by controlling a three- state gate circuit connected to each bit line of a data bus with output of a gate which makes the logical product of an output of address decoder and a write strobe signal. CONSTITUTION:An address signal is put on an address bus AB in one write cycle period, and an address decoder AD generates a decode output in the period corresponding to an address. When a write strobe signal WS which is outputted with a timing in which an operation is regulated arrives, the output of a NAND gate G becomes an L level, and the L level is impressed on the inhibiting terminals of three-states gate circuits T0-Ti, making conduct the circuits T0-Ti. Therefore, when bit lines D0-Di of a data bus DB are L levels, the output of L level is generated during the signal WS exists as the output, and when they are H levels, the output keeps the H level and no output pulse is generated.</p>
申请公布号 JPS62115511(A) 申请公布日期 1987.05.27
申请号 JP19850255907 申请日期 1985.11.15
申请人 FUJITSU LTD 发明人 SUMIDA TETSUAKI;SERIKAWA ATSUO;KAMIO YOSHIHARU
分类号 G06F3/00;G06F1/04 主分类号 G06F3/00
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