发明名称 BIT SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To perform bit synchronization independently of duty distortion by detecting the form of the duty distortion of a non-return-to-zero (NRZ) signal to select one clock from the kinds of clocks synchronized with the level change of the NRZ signal. CONSTITUTION:The direct NRZ signal from a terminal 101 and the NRZ signal passing an inverter A01 are supplied to FFs A02 and A03 respectively. The clock synchronized with the rise of the NRZ signal from zero to one is supplied to a data terminal D of the FF A02, and the Q output of the FF A02 goes to a high level synchronously with the rise of the NRZ signal. A bit signal synchronized with the rise of the NRZ signal is outputted from a synchronizing circuit A04. Similarly, a bit signal synchronized with the fall of the NRZ signal is outputted by the FF A03 whose data terminal D the clock synchronized with the fall of the NRZ signal is applied to, a bit synchronizing circuit A05, etc. Phases of both bit signals are compared with each other by an FF A06, and one bit signal having the leading phase is outputted. By this constitution, bit synchronization of the NRZ signal having 2:1 or 1:2 duty distortion is possible.
申请公布号 JPS62114348(A) 申请公布日期 1987.05.26
申请号 JP19850255579 申请日期 1985.11.13
申请人 NEC CORP 发明人 NAKAJIMA TAKESHI
分类号 H03K5/00;H03M5/06;H04L7/02 主分类号 H03K5/00
代理机构 代理人
主权项
地址