| 摘要 |
PURPOSE:To prevent a threshold voltage from varying by forming the first conductivity type high density impurity region having a impurity density higher than a substrate and a shorter width than the average free step of carrier between a drain region and a channel region to eliminate the adverse influence of impact ions. CONSTITUTION:A gate electrode 14 is formed through a gate oxide film 13 on a P-type Si substrate 11, and N<+> type layer (source, drain regions) 18a, 18b due to N-type impurity diffusion are formed outside the channel region under the electrode 14. The same conductivity type P<+> layer (high density impurity regions) 16a, 16b as the substrate 11 are formed between the regions 18a, 18b and a channel region. Here, the widths of the regions 16a, 16b are shorter than the average free step of a carrier.
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