| 摘要 |
PURPOSE:To scale down cell size, and to improve the deterioration of element characteristics by etching an silicon substrate by forming specific layers onto a semiconductor substrate in succession and simultaneously shaping each gate through a self-alignment process. CONSTITUTION:A gate thermal oxide film 2, a first phosphorus-doped polysilicon layer 3, an silicon thermal oxide film 4 and a second phosphorus-doped polysilicon layer 5 are formed onto a P-type silicon substrate 1 in succession, and desired resist patterns 6 are shaped by using an optical exposure technique (a). The second phosphorus-doped polysilicon layer 5 is etched, employing the resist patterns 6 as masks, etching is conducted, using each layer as masks successively, and the gate oxide film 2 is etched selectively, thus completing a series of processing for gate sections. The first phosphorus-doped polysilicon 3 functions as a floating gate 10 in a memory transistor section and as a gate 12 in a selective transistor section at that time (b), (c). Accordingly, the silicon substrate in element regions is not etched, thus improving the deterioration, etc. of element characteristics.
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