| 摘要 |
Circuitry for computing the square root of a number wherein the input number is partitioned into digit pairs left and right of the radix point. Pairs of zeros are added after the radix point for each digit of the desired precision. The most significant zero digit pairs are skipped to the first digit pair which is not zero, accordingly the first answer bit is a 1. A residue is formed by subtracting the 1 from the digit pair, multiplying by 4, and adding the next most significant digit pair. The procedure is repeated for subsequent bit pairs by defining trial divisors and determining residue values. |
