| 摘要 |
PURPOSE:To execute a read operation and a write operation by the same cycle, and to execute said operations at high speed by providing an address varying means on a source memory and a receive memory, respectively. CONSTITUTION:In order that a CPU6 executes a DMA transfer, the head address of a source memory 1 is set to a source address counter 3, and the head address of a receive memory 2 is set to a receive address counter 4. Also, the number of DMA transfer words is set to a word counter 5. In this way, by bringing these three counters to a count start at the same time, the read operation and the write operation can be executed by the same cycle.
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