发明名称 EXTERNAL SYNCHRONIZING TYPE SAMPLE HOLDING CIRCUIT
摘要 PURPOSE:To surely output creset value of desired input signals even when the input signals have much distortion in TDMA system by generating a signal that determines sampling timing of input signals making an external synchronizing signal a trigger. CONSTITUTION:An external synchronizing signal is inputted from a terminal 2 to a delay time adjusting circuit 3, and delay time of input signals is adjusted. The output signals are inputted to a sampling time determining circuit 4 for determining time for sampling detected signals. The circuit 4 adjusts sampling time avoiding unnecessary generated signals. On the other hand, input signals from a terminal 1 are inputted to a peak value holding circuit 5. The circuit 5 detects the input signal level at this point of time and holds detected level until a sampling time adjusting signal is received next. The held signal is outputted as the crest value of detected signals.
申请公布号 JPS62114199(A) 申请公布日期 1987.05.25
申请号 JP19850253802 申请日期 1985.11.14
申请人 NEC CORP;NEC ENG LTD 发明人 TACHIKA TOSHIAKI;SATO YASUSHI
分类号 H04J3/00;G11C27/02;H03K7/02 主分类号 H04J3/00
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