| 摘要 |
<p>PURPOSE:To reduce a signal propagation delay time by connecting a signal amplifier circuit in parallel in a signal line having a large signal propagation delay time. CONSTITUTION:When a mode enters into an active mode, a phiB becomes Vdd, but, a word line still keeps 0V, and a transistor TP1 remains at off-state and a node 10 keeps a Vdd level, and a transistor TP1 also keeps the off-state. A selected word line w1 is led gradually to the Vdd level, and when the level of the word line arrives at the threshold voltage of the transistor TN2, the transistor TN2 is turned on, and the word line is pulled up by the phiB. Next, when the phiB is trailed simultaneously with a signal trailing the word line, a triggering is performed and when the phiB becomes 0V, a TP2 is turned on, but, the leading of the node 10 can be performed gradually by setting an on- resistance. Thus, since the TP1 keeps an on-state for a while, the potential of the word line is pulled by the 0V of the phiB and consequently, the trailing of the word line becomes steep.</p> |
