| 摘要 |
PURPOSE:To minimize a linking distortion by adding a prescribed clock control circuit in a clock phase locking system for receiving a dot-interlaced image signal. CONSTITUTION:A digital input image signal 32 is supplied to the clock control circuit 10. Then, a maximum value selector 14 selectively selects a linking detecting additional pulse part sent at every period and holds the maximum value of the linking. A comparator 17 compares the current value out of the outputs of a selector 14 with a value obtained before one period. A reversible counter 22 executes counting based on control signals from AND gates 20, 21 which are obtained based on said compared result. A demultiplexer 23 selects one of output groups of a delay line 24 with taps which is specified by the counter 22. The output 25 of the demultiplexer 23 is applied to an A/D converter for digitizing the input image signal. Consequently, the linking distortion can be minimized.
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