| 摘要 |
PURPOSE:To avoid mistake by providing a delay circuit, a latch circuit corresponding to it and a clock generation LSI provided to an address generation circuit so as to control the adjustment electrically entirely. CONSTITUTION:A data given to a latch circuit group 2 is stored in a storage circuit 5, an address generation circuit 3 is operated synchronously with an external clock signal and the data in the circuit 5 is inputted to the circuit group 2 and a clock signal is sent through a terminal T1 sequentially from the corresponding delay circuit 1. In this case, the waveform of the clock is adjusted next. That is, the latch data is inputted from a terminal T3 of the circuit group 2, an address data is inputted and adjusted from a terminal T4, and when a desired clock waveform is obtained by the latch data, a write signal is sent from a terminal T5 for the write. The operation as above is repeated and the latch data subject to entire adjustment is stored in the device 5. |
