| 摘要 |
PURPOSE:To minimize a linking distortion by adding a prescribed linking detector in a clock phase locking system for receiving a dot-interlaced image signal. CONSTITUTION:A digital input video signal 24 is supplied to a linking detector 10. Then, a maximum value selector 14 selectively extracts a linking detecting additional pulse part sent at every fixed period and holds the maximum value of the linking. A comparator 17 compares a current value out of the outputs of a selector 14 with a value obtained before one period. A reversible counter 22 executes the counting based on control signals outputted from AND gates 20, 21 which are obtained based on said compared result. The output of the counter 22 is converted into an analog value by an A/D converter 23 and applied to an adder in the clock phase locking system. Consequently, the linking can be minimized.
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